// riscv_npu_soc.sv
`timescale 1ns/1ps
module riscv_npu_soc (
  input  logic        clk,
  input  logic        rst_n,

  // JTAG
  input  logic        tck, tms, tdi,
  output logic        tdo,

  // APB Debug
  input  logic [31:0] apb_paddr,
  input  logic        apb_psel, apb_penable, apb_pwrite,
  input  logic [31:0] apb_pwdata,
  output logic [31:0] apb_prdata,
  output logic        apb_pready, apb_pslverr,

  // UART (调试输出)
  input  logic        uart_rxd,
  output logic        uart_txd
);

  // AXI4-Lite 信号
  logic [31:0] m_axi_awaddr, m_axi_araddr, m_axi_wdata, m_axi_rdata;
  logic        m_axi_awvalid, m_axi_arvalid, m_axi_wvalid, m_axi_rvalid;
  logic        m_axi_awready, m_axi_arready, m_axi_wready, m_axi_rready;
  logic        m_axi_bvalid, m_axi_bready;
  logic [3:0]  m_axi_wstrb;
  logic [1:0]  m_axi_bresp, m_axi_rresp;

  // 实例化 NPU 核心
  riscv_npu_top u_top (
    .clk(clk), .rst_n(rst_n),
    .tck(tck), .tms(tms), .tdi(tdi), .tdo(tdo),
    .paddr(apb_paddr), .psel(apb_psel), .penable(apb_penable),
    .pwrite(apb_pwrite), .pwdata(apb_pwdata),
    .prdata(apb_prdata), .pready(apb_pready), .pslverr(apb_pslverr),

    .axi_awaddr(m_axi_awaddr), .axi_awvalid(m_axi_awvalid), .axi_awready(m_axi_awready),
    .axi_wdata(m_axi_wdata),   .axi_wstrb(m_axi_wstrb),   .axi_wvalid(m_axi_wvalid), .axi_wready(m_axi_wready),
    .axi_bresp(m_axi_bresp),   .axi_bvalid(m_axi_bvalid), .axi_bready(m_axi_bready),
    .axi_araddr(m_axi_araddr), .axi_arvalid(m_axi_arvalid), .axi_arready(m_axi_arready),
    .axi_rdata(m_axi_rdata),   .axi_rresp(m_axi_rresp),   .axi_rvalid(m_axi_rvalid), .axi_rready(m_axi_rready)
  );

  // AXI Interconnect (1 Master → 2 Slaves)
  axi_interconnect_1x2 u_axi_ic (
    .aclk(clk), .aresetn(rst_n),
    .s_axi_awaddr(m_axi_awaddr), .s_axi_awvalid(m_axi_awvalid), .s_axi_awready(m_axi_awready),
    .s_axi_wdata(m_axi_wdata),   .s_axi_wstrb(m_axi_wstrb),   .s_axi_wvalid(m_axi_wvalid), .s_axi_wready(m_axi_wready),
    .s_axi_bresp(m_axi_bresp),   .s_axi_bvalid(m_axi_bvalid), .s_axi_bready(m_axi_bready),
    .s_axi_araddr(m_axi_araddr), .s_axi_arvalid(m_axi_arvalid), .s_axi_arready(m_axi_arready),
    .s_axi_rdata(m_axi_rdata),   .s_axi_rresp(m_axi_rresp),   .s_axi_rvalid(m_axi_rvalid), .s_axi_rready(m_axi_rready),

    // Slave 0: BRAM (0x0000_0000 - 0x0000_3FFF)
    .m00_axi_awaddr(), .m00_axi_awvalid(), .m00_axi_awready(1'b1),
    .m00_axi_wdata(),  .m00_axi_wstrb(),  .m00_axi_wvalid(), .m00_axi_wready(1'b1),
    .m00_axi_bresp(2'b00), .m00_axi_bvalid(1'b0),
    .m00_axi_araddr(), .m00_axi_arvalid(), .m00_axi_arready(1'b1),
    .m00_axi_rdata(),  .m00_axi_rresp(2'b00), .m00_axi_rvalid(1'b0),

    // Slave 1: NPU CSR (0x1000_0000+)
    .m01_axi_awaddr(), .m01_axi_awvalid(), .m01_axi_awready(1'b1),
    .m01_axi_wdata(),  .m01_axi_wstrb(),  .m01_axi_wvalid(), .m01_axi_wready(1'b1),
    .m01_axi_bresp(2'b00), .m01_axi_bvalid(1'b0),
    .m01_axi_araddr(), .m01_axi_arvalid(), .m01_axi_arready(1'b1),
    .m01_axi_rdata(),  .m01_axi_rresp(2'b00), .m01_axi_rvalid(1'b0)
  );

  // UART (printf debug)
  logic [7:0] uart_data;
  logic       uart_start;
  uart_tx u_uart (
    .clk(clk), .rst_n(rst_n),
    .txd(uart_txd),
    .data(uart_data),
    .start(uart_start)
  );

  // 简单 printf 例程（可通过 APB 触发）
  // 在 C 程序中使用 putchar()

endmodule